SiC’s properties have been identified as advantageous for power device fabrication. Despite lower defect densities and substrate costs, SiC is still not as mature or consistent as silicon. However, significant progress is being made in understanding the cause-and-effect relationships between variations and defects in SiC substrates and devices.
There’s a promise of silicon carbide (SiC driver) over conventional silicon for the design of next-generation power electronics devices, but widespread adoption of this high-performance compound semiconductor has been limited due to several misconceptions about SiC substrate costs, the material’s physical quirks, and the past difficulty of controlling defect density.
None of these challenges, however, are insurmountable, and the development of low-defect, large-diameter SiC wafers is now on the horizon. Now, as it nears commercial maturity, it’s worth looking into integration and design considerations for a SiC driver.
SiC Cost Factors
Currently, SiC device work is based on substrates with diameters of 76 and 100 mm. When compared to silicon devices manufactured on 150-200 mm diameter wafers, the cost of manufacturing a device with SiC is more expensive in part because smaller substrates mean lower die counts and additional costs for handling.
The recent introduction of SiC wafers with a diameter of 150 mm will cut manufacturing costs for SiC power devices by more than half and eliminate special handling costs.
The remaining question is whether SiC devices can be manufactured at a low enough cost to produce a device capable of competing with silicon power devices in system applications. Because of the properties of SiC, it is possible to design power devices with a smaller area or, to put it another way, devices with a higher current density. When compared to a traditional silicon power device design, this advantage allows you to populate the wafer with a greater number of dies.
Obviously, as the number of dies per wafer increases, so should the cost. The relationship between substrate costs and device manufacturing costs does not scale directly when die size is a variable, which is less obvious.
For a fixed wafer diameter, the cost of the epiwafer (Wafer$) combined with the cost of executing the manufacturing and testing process (Fab$) represents the total manufacturing costs.
According to good manufacturing economics, total costs should be constant in relation to the number of dies per wafer:
Constant = (Wafer$ + Fabric$)/(Device Count) (1)
Fab$ costs generally do not change as the price of the wafer increases. However, as wafer prices rise, the cost of producing SiC devices will rise as well, unless a higher die count is achieved.
The Effect of SiC Defects on Device Performance
Recent advancements in SiC crystal led to the reduction in defects. Historically, the quality of newer, larger wafers has been lower than in previous generations, but it has gradually improved with demand over time. These 150-mm diameter SiC wafers may help lower the SiC device costs, but they can still be a costly development platform.
To fully benefit from 150-mm diameter SiC substrates, these substrates must be ready to support high production yields. Defects in the larger diameter material must be maintained or improved to provide a smooth transition from smaller wafer diameters. Second, the performance of the epitaxial film parameters and the device fabrication process must be adequate to utilize the entire 150-mm wafer surface.
Micropipes are a well-known killer defect in SiC wafers. Dow Corning’s crystal technology was developed to achieve 150-mm crystals while maintaining low micropipe performance at 1/cm2. Many designers are concerned about screw dislocations in larger devices, and basal plane defects in bipolar device designs.
Surface defects produced during the chemical vapor deposition (CVD) epitaxy process limit the yield of SiC devices as well. Currently, this is the most likely defect to limit or kill device performance. The current state-of-the-art in epitaxy defects varies depending on the film thickness target, with a defect density of 1.5-2.0/cm2 being typical for wafers used in applications with a blocking voltage of less than 2 kV.
Recently developed batch manufacturing epitaxy technology allows for the integration of 150-mm wafers. This capability ensures that epitaxy defect performance is consistent between the 100-mm and 150-mm product generations.
Design and Fabrication
It is critical to take advantage of SiC’s higher voltage and thermal conductivity properties when compared to silicon for successful device and system designs. Other properties of SiC wafers must also be understood in order for the device to perform well:
SiC wafers are transparent, which can cause issues with photolithography using steppers, automated defect detection, and automated wafer handling. Automated defect detection may misidentify features beneath the surface as surface defects. Sensors set up for opaque materials in wafer handling may respond incorrectly, resulting in wafer breakage during load/unload events.
- Dopant Incorporation
Dopant atom implantation and activation in SiC is more difficult than in silicon. When compared to silicon, dopant diffusion is extremely small.
Temperatures above 1500°C are required for implant activation in SiC, and the wafer surface should be well-protected during this process to avoid roughening. Silicon may have a lower activation efficiency, and total activation varies with total dopant concentration.
- Substrate Resistivity
The resistivity of SiC substrates is higher than that of silicon substrates. Because the epitaxy thickness used in SiC designs is small in comparison to silicon, the SiC substrate can contribute more to a device’s series resistance.
Forming ohmic contacts on SiC wafers frequently necessitates a high temperature anneal (T> 800°C). Because the anneal temperature may have an adverse effect on subsequent device processes, this step must be performed early in the device fabrication flow.
Process optimization is critical to achieving optimum low forward voltage drop performance in SiC MOSFETs and minimizing series resistance effects caused by the ohmic contact.
Polycrystalline surface defects that form on the wafer surface during epitaxy are the most serious defect associated with SiC devices. These lethal flaws are easily detectable using automated optical spectrometry techniques. Surface protrusion from defects can cause comet formation in photoresist layers, resulting in fabrication failures in areas of the wafer not affected by the defect.
Photoresist inspection is an important in-process step for identifying potential fabrication issues. Other flaws that can impair device performance may also exist. Polishing processes can cause very minor damage to the epitaxy surface, resulting in shallow linear defects that will be decorated during the metallization steps. These flaws can cause hot spots on the device in the region beneath the gate or in the edge termination areas.
- Device Attributes
SiC MOSFETs and similar devices exhibit positive temperature coefficients for the forward bias on state resistance. Many results have been published in the literature, and device suppliers’ application notes state that SiC devices have lower conduction and switching losses than silicon-based devices.
There are several models that can be used when designing SiC devices. But, despite these advancements, the models are continuously showing offsets from experimental data that are measured on fabricated devices. It’s critical to ensure that the material properties entered into the model are consistent with those of the materials used to fabricate the devices.
Many collaborations and partnerships focused on materials characterization and device fabrication, as well as expertise in product specification and application development, can help semiconductor device manufacturers accelerate their efforts to implement SiC in next-generation power devices and systems.